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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-07-22 12:15:22 +0100 |
|---|---|---|
| committer | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-07-23 18:11:11 +0100 |
| commit | 67b4ce06e07fde80d5ac11cad4d673c501bdd421 (patch) | |
| tree | 26ba1373941ac0c83ff10a1edc530053ad1d4dec /techlibs/intel/common | |
| parent | c6d8692c9711e4b65aa89ad60986c9df7e053fc7 (diff) | |
| download | yosys-67b4ce06e07fde80d5ac11cad4d673c501bdd421.tar.gz yosys-67b4ce06e07fde80d5ac11cad4d673c501bdd421.tar.bz2 yosys-67b4ce06e07fde80d5ac11cad4d673c501bdd421.zip | |
intel: Map M9K BRAM only on families that have it
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.
Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
Diffstat (limited to 'techlibs/intel/common')
| -rw-r--r-- | techlibs/intel/common/brams_m9k.txt (renamed from techlibs/intel/common/brams.txt) | 0 | ||||
| -rw-r--r-- | techlibs/intel/common/brams_map_m9k.v (renamed from techlibs/intel/common/brams_map.v) | 0 |
2 files changed, 0 insertions, 0 deletions
diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams_m9k.txt index 3bf21afc9..3bf21afc9 100644 --- a/techlibs/intel/common/brams.txt +++ b/techlibs/intel/common/brams_m9k.txt diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map_m9k.v index d0f07c1de..d0f07c1de 100644 --- a/techlibs/intel/common/brams_map.v +++ b/techlibs/intel/common/brams_map_m9k.v |