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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-09 10:18:08 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-09 10:18:08 +0200 |
| commit | f9d023c53fedd96ec1b9d3a93d0448291a1f2527 (patch) | |
| tree | fcfcc822bef8f91d76d3a3714d8363d5617e27de /techlibs/intel/common | |
| parent | 13eb47c6927766a34256b98538d148e04cc87c18 (diff) | |
| download | yosys-f9d023c53fedd96ec1b9d3a93d0448291a1f2527.tar.gz yosys-f9d023c53fedd96ec1b9d3a93d0448291a1f2527.tar.bz2 yosys-f9d023c53fedd96ec1b9d3a93d0448291a1f2527.zip | |
Add src attribute to extra cells generated by proc_dlatch
Diffstat (limited to 'techlibs/intel/common')
0 files changed, 0 insertions, 0 deletions