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| author | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-04 06:31:09 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-04 06:31:09 +0100 |
| commit | 10014e2643cdedd2050f072eb5d1b8d01dccc406 (patch) | |
| tree | 2841ecc585a9d08aa510cebdab74e03b93e0aa11 /techlibs/intel/cycloneiv | |
| parent | 2ec6d832dc07a68157721715785d469feabbb6ed (diff) | |
| download | yosys-10014e2643cdedd2050f072eb5d1b8d01dccc406.tar.gz yosys-10014e2643cdedd2050f072eb5d1b8d01dccc406.tar.bz2 yosys-10014e2643cdedd2050f072eb5d1b8d01dccc406.zip | |
xilinx: Add models for LUTRAM cells. (#1537)
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