Clean whitespace and permissions in techlibs/intel

1 files changed, 14 insertions, 14 deletions

diff --git a/techlibs/intel/cycloneive/cells_sim.v b/techlibs/intel/cycloneive/cells_sim.v
index 23d06bc1e..f17b86fdf 100755..100644
--- a/techlibs/intel/cycloneive/cells_sim.v
+++ b/techlibs/intel/cycloneive/cells_sim.v
@@ -25,21 +25,21 @@ module GND (output G);
 endmodule // GND
 
 /* Altera Cyclone IV (E) devices Input Buffer Primitive */
-module cycloneive_io_ibuf 
+module cycloneive_io_ibuf
   (output o, input i, input ibar);
    assign ibar = ibar;
    assign o    = i;
 endmodule // fiftyfivenm_io_ibuf
 
 /* Altera Cyclone IV (E)  devices Output Buffer Primitive */
-module cycloneive_io_obuf 
+module cycloneive_io_obuf
   (output o, input i, input oe);
    assign o  = i;
    assign oe = oe;
 endmodule // fiftyfivenm_io_obuf
 
 /* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
-module cycloneive_lcell_comb 
+module cycloneive_lcell_comb
   (output combout, cout,
    input dataa, datab, datac, datad, cin);
 
@@ -112,7 +112,7 @@ module cycloneive_lcell_comb
 endmodule // cycloneive_lcell_comb
 
 /* Altera D Flip-Flop Primitive */
-module dffeas 
+module dffeas
   (output q,
    input d, clk, clrn, prn, ena,
    input asdata, aload, sclr, sload);
@@ -124,7 +124,7 @@ module dffeas
    reg   q_tmp;
    wire  reset;
    reg [7:0] debug_net;
-   
+
    assign reset       = (prn && sclr && ~clrn && ena);
    assign q           = q_tmp & 1'b1;
 
@@ -133,7 +133,7 @@ module dffeas
       else q_tmp <= d;
    end
    assign q = q_tmp;
-   
+
 endmodule // dffeas
 
 /* Cyclone IV E altpll clearbox model */
@@ -174,9 +174,9 @@ module cycloneive_pll
    parameter bandwidth                     = 0;
    parameter bandwidth_type                = "auto";
    parameter use_dc_coupling               = "false";
-   parameter lock_high = 0; 
-   parameter lock_low = 0;  
-   parameter lock_window_ui                = "0.05"; 
+   parameter lock_high = 0;
+   parameter lock_low = 0;
+   parameter lock_window_ui                = "0.05";
    parameter test_bypass_lock_detect       = "off";
    parameter clk0_output_frequency         = 0;
    parameter clk0_multiply_by              = 0;
@@ -255,16 +255,16 @@ module cycloneive_pll
    parameter c4_test_source = -1;
    parameter vco_multiply_by = 0;
    parameter vco_divide_by = 0;
-   parameter vco_post_scale = 1; 
+   parameter vco_post_scale = 1;
    parameter vco_frequency_control = "auto";
    parameter vco_phase_shift_step = 0;
    parameter charge_pump_current = 10;
-   parameter loop_filter_r = "1.0";   
-   parameter loop_filter_c = 0;    
+   parameter loop_filter_r = "1.0";
+   parameter loop_filter_c = 0;
    parameter pll_compensation_delay = 0;
    parameter lpm_type = "cycloneive_pll";
    parameter phase_counter_select_width = 3;
- 
+
    input [1:0] inclk;
    input       fbin;
    input       clkswitch;
@@ -288,5 +288,5 @@ module cycloneive_pll
    output                                   phasedone;
    output                                   vcooverrange;
    output                                   vcounderrange;
-   
+
 endmodule // cycloneive_pll