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author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-10-04 17:01:30 -0700 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-10-05 16:23:49 +0200 |
commit | 50bcd9a728ff89f220873b3345c4e18a65c4a37f (patch) | |
tree | ff7b306d49b46ec25b7bfac26ca9ace82302a3f0 /techlibs/intel/cyclonev | |
parent | fc3378916dbaf46018a99571ef190189088c225c (diff) | |
download | yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.gz yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.bz2 yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.zip |
Clean whitespace and permissions in techlibs/intel
Diffstat (limited to 'techlibs/intel/cyclonev')
-rw-r--r--[-rwxr-xr-x] | techlibs/intel/cyclonev/cells_arith.v | 8 | ||||
-rw-r--r--[-rwxr-xr-x] | techlibs/intel/cyclonev/cells_map.v | 110 | ||||
-rw-r--r--[-rwxr-xr-x] | techlibs/intel/cyclonev/cells_sim.v | 20 |
3 files changed, 69 insertions, 69 deletions
diff --git a/techlibs/intel/cyclonev/cells_arith.v b/techlibs/intel/cyclonev/cells_arith.v index 470b686bb..89fb4561f 100755..100644 --- a/techlibs/intel/cyclonev/cells_arith.v +++ b/techlibs/intel/cyclonev/cells_arith.v @@ -45,10 +45,10 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] C = {COx, CI}; - + /* Start implementation */ (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - + genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice if(i==Y_WIDTH-1) begin @@ -61,5 +61,5 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); endgenerate /* End implementation */ assign X = AA ^ BB; - -endmodule + +endmodule diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v index b3927ea4a..9fe8db2da 100755..100644 --- a/techlibs/intel/cyclonev/cells_map.v +++ b/techlibs/intel/cyclonev/cells_map.v @@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; wire E_i = ~ E; dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); @@ -60,89 +60,89 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function - end + end else if (WIDTH == 2) begin - cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(1'b1), - .datad(1'b1), - .datae(1'b1), - .dataf(1'b1), + .datad(1'b1), + .datae(1'b1), + .dataf(1'b1), .datag(1'b1)); - end + end else if(WIDTH == 3) begin - cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off")) + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(1'b1), - .datae(1'b1), - .dataf(1'b1), + .datad(1'b1), + .datae(1'b1), + .dataf(1'b1), .datag(1'b1)); - end + end else if(WIDTH == 4) begin - cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off")) + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(A[3]), - .datae(1'b1), - .dataf(1'b1), + .datad(A[3]), + .datae(1'b1), + .dataf(1'b1), .datag(1'b1)); - end + end else - if(WIDTH == 5) begin + if(WIDTH == 5) begin cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(1'b1), + .datad(A[3]), + .datae(A[4]), + .dataf(1'b1), .datag(1'b1)); - end + end else if(WIDTH == 6) begin cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(A[5]), + .datad(A[3]), + .datae(A[4]), + .dataf(A[5]), .datag(1'b1)); - end + end else if(WIDTH == 7) begin cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(A[5]), + .datad(A[3]), + .datae(A[4]), + .dataf(A[5]), .datag(A[6])); - end + end else wire _TECHMAP_FAIL_ = 1; endgenerate diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v index 363310e54..5ecdabcfc 100755..100644 --- a/techlibs/intel/cyclonev/cells_sim.v +++ b/techlibs/intel/cyclonev/cells_sim.v @@ -25,23 +25,23 @@ module GND (output G); endmodule // GND /* Altera Cyclone V devices Input Buffer Primitive */ -module cyclonev_io_ibuf +module cyclonev_io_ibuf (output o, input i, input ibar); assign ibar = ibar; assign o = i; endmodule // cyclonev_io_ibuf /* Altera Cyclone V devices Output Buffer Primitive */ -module cyclonev_io_obuf +module cyclonev_io_obuf (output o, input i, input oe); assign o = i; assign oe = oe; endmodule // cyclonev_io_obuf /* Altera Cyclone V LUT Primitive */ -module cyclonev_lcell_comb +module cyclonev_lcell_comb (output combout, cout, sumout, shareout, - input dataa, datab, datac, datad, + input dataa, datab, datac, datad, input datae, dataf, datag, cin, input sharein); @@ -59,8 +59,8 @@ module cyclonev_lcell_comb // Extended mode uses mux to define the output wire mux_0, mux_1; // Input for hold the shared LUT mode value - wire shared_lut_alm; - + wire shared_lut_alm; + // Simulation model of 4-input LUT function lut4; input [15:0] mask; @@ -75,7 +75,7 @@ module cyclonev_lcell_comb lut4 = dataa ? s1[1] : s1[0]; end endfunction // lut4 - + // Simulation model of 5-input LUT function lut5; input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer. @@ -119,7 +119,7 @@ endmodule // cyclonev_lcell_comb /* Altera D Flip-Flop Primitive */ -module dffeas +module dffeas (output q, input d, clk, clrn, prn, ena, input asdata, aload, sclr, sload); @@ -131,7 +131,7 @@ module dffeas reg q_tmp; wire reset; reg [7:0] debug_net; - + assign reset = (prn && sclr && ~clrn && ena); assign q = q_tmp & 1'b1; @@ -140,5 +140,5 @@ module dffeas else q_tmp <= d; end assign q = q_tmp; - + endmodule // dffeas |