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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:12:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:12:34 -0700 |
| commit | faa2d6fc1c4bc10cda96c2dc3721df209d2d2117 (patch) | |
| tree | 717d4dbb5baed5537b922c93002d075cda49d96e /techlibs/intel/max10/cells_sim.v | |
| parent | aeee9dcad7f6d5fc30f133a89c5dd6f209283c11 (diff) | |
| download | yosys-faa2d6fc1c4bc10cda96c2dc3721df209d2d2117.tar.gz yosys-faa2d6fc1c4bc10cda96c2dc3721df209d2d2117.tar.bz2 yosys-faa2d6fc1c4bc10cda96c2dc3721df209d2d2117.zip | |
Constrain wreduce only if wide mux
Diffstat (limited to 'techlibs/intel/max10/cells_sim.v')
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