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| author | whitequark <whitequark@whitequark.org> | 2020-04-05 02:06:26 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-09 04:08:36 +0000 |
| commit | 01e6850bd3b9c884a0ea9785ff5ff1ffd59b82e2 (patch) | |
| tree | 98e6bc8c109ecafe2f8125848067649b55eca1b6 /techlibs/intel/synth_intel.cc | |
| parent | fb0270b75258fa58cbf0594873721c88964f69a5 (diff) | |
| download | yosys-01e6850bd3b9c884a0ea9785ff5ff1ffd59b82e2.tar.gz yosys-01e6850bd3b9c884a0ea9785ff5ff1ffd59b82e2.tar.bz2 yosys-01e6850bd3b9c884a0ea9785ff5ff1ffd59b82e2.zip | |
write_cxxrtl: improve writable memory handling.
This commit reduces space and time overhead for writable memories
to O(write port count) in both cases; implements handling for write
port priorities; and simplifies runtime representation of memories.
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
0 files changed, 0 insertions, 0 deletions