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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-16 15:28:29 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-16 15:28:29 +0100 |
| commit | 19ca4e2ac3f9a4d374299e914ac08c47813f909b (patch) | |
| tree | a322b3e9798e404d26b1c623d60cf28687173bbc /techlibs/intel/synth_intel.cc | |
| parent | 556341a77fccd990fa8c06c78b2b41a956b9b98f (diff) | |
| parent | a9baee4b24a2e2d854d96b9d38e53f3cc4e1262a (diff) | |
| download | yosys-19ca4e2ac3f9a4d374299e914ac08c47813f909b.tar.gz yosys-19ca4e2ac3f9a4d374299e914ac08c47813f909b.tar.bz2 yosys-19ca4e2ac3f9a4d374299e914ac08c47813f909b.zip | |
Merge pull request #722 from whitequark/rename_src
rename: add -src, for inferring names from source locations
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
0 files changed, 0 insertions, 0 deletions