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| author | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-04 08:44:08 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-04 08:44:08 +0100 |
| commit | 2abe38e73e51204976129c776447c2d40578c32f (patch) | |
| tree | a98c132f23c89e7389e904c8b88b87dc83ec42c2 /techlibs/intel/synth_intel.cc | |
| parent | 10014e2643cdedd2050f072eb5d1b8d01dccc406 (diff) | |
| download | yosys-2abe38e73e51204976129c776447c2d40578c32f.tar.gz yosys-2abe38e73e51204976129c776447c2d40578c32f.tar.bz2 yosys-2abe38e73e51204976129c776447c2d40578c32f.zip | |
iopadmap: Refactor and fix tristate buffer mapping. (#1527)
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
0 files changed, 0 insertions, 0 deletions