diff options
| author | Claire Wolf <clifford@clifford.at> | 2020-01-29 15:25:03 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-29 15:25:03 +0100 |
| commit | 5f53ea2b5b6b956b1743ad1b3aab11d2c311ab52 (patch) | |
| tree | fce673ef478d1769abd076a021d89ad1928868d3 /techlibs/intel/synth_intel.cc | |
| parent | 177a7cb23e5ae8f3879d3b33629bfad0139a0162 (diff) | |
| parent | 5c2508cef82d86cebff3d008962fde6a0e49d10e (diff) | |
| download | yosys-5f53ea2b5b6b956b1743ad1b3aab11d2c311ab52.tar.gz yosys-5f53ea2b5b6b956b1743ad1b3aab11d2c311ab52.tar.bz2 yosys-5f53ea2b5b6b956b1743ad1b3aab11d2c311ab52.zip | |
Merge pull request #1659 from YosysHQ/clifford/experimental
Add log_experimental() and experimental() API and "yosys -x"
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 2ebb8bf50..3689df70e 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -26,7 +26,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct SynthIntelPass : public ScriptPass { - SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") {} + SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { experimental(); } void help() YS_OVERRIDE { |