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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 15:58:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 15:58:01 -0700 |
| commit | cea7441d8ae7df8d22f510e6a101ec46a9d7751e (patch) | |
| tree | 8067ba09ecfaf6d9cf32e8ed9adba42be27b86a4 /techlibs/intel/synth_intel.cc | |
| parent | c865559f9540c29cb9c6302edc8b4a2620c0b49d (diff) | |
| parent | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff) | |
| download | yosys-cea7441d8ae7df8d22f510e6a101ec46a9d7751e.tar.gz yosys-cea7441d8ae7df8d22f510e6a101ec46a9d7751e.tar.bz2 yosys-cea7441d8ae7df8d22f510e6a101ec46a9d7751e.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 639cba2c2..09c9ba3af 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -48,6 +48,8 @@ struct SynthIntelPass : public ScriptPass { log(" -vqm <file>\n"); log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); + log(" Note that this backend has not been tested and is likely incompatible\n"); + log(" with recent versions of Quartus.\n"); log("\n"); log(" -vpr <file>\n"); log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n"); @@ -108,6 +110,7 @@ struct SynthIntelPass : public ScriptPass { } if (args[argidx] == "-vqm" && argidx + 1 < args.size()) { vout_file = args[++argidx]; + log_warning("The Quartus backend has not been tested recently and is likely incompatible with modern versions of Quartus.\n"); continue; } if (args[argidx] == "-vpr" && argidx + 1 < args.size()) { |