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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-02 14:47:18 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-02 14:47:18 +0100 |
| commit | 16bb823db8116ea2da2c659f8b9b2e9e2b9f2fbf (patch) | |
| tree | 61971fdccdc1bb24169d78d0193eccc957232536 /techlibs/intel | |
| parent | 4b9f619349e6b7452739631635ab3b5a4d94b522 (diff) | |
| parent | efa278e232d20ea080743801bd91d55ec62955cf (diff) | |
| download | yosys-16bb823db8116ea2da2c659f8b9b2e9e2b9f2fbf.tar.gz yosys-16bb823db8116ea2da2c659f8b9b2e9e2b9f2fbf.tar.bz2 yosys-16bb823db8116ea2da2c659f8b9b2e9e2b9f2fbf.zip | |
Merge pull request #769 from whitequark/typos
Fix typographical and grammatical errors and inconsistencies
Diffstat (limited to 'techlibs/intel')
| -rw-r--r-- | techlibs/intel/cyclonev/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v index 5ecdabcfc..fa27c2c8e 100644 --- a/techlibs/intel/cyclonev/cells_sim.v +++ b/techlibs/intel/cyclonev/cells_sim.v @@ -54,7 +54,7 @@ module cyclonev_lcell_comb // Internal variables // Sub mask for fragmented LUTs wire [15:0] mask_a, mask_b, mask_c, mask_d; - // Independant output for fragmented LUTs + // Independent output for fragmented LUTs wire output_0, output_1, output_2, output_3; // Extended mode uses mux to define the output wire mux_0, mux_1; |