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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-02 12:48:07 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-02 12:48:07 -0800 |
| commit | 3012e9eebc2950b996d17a018bb2e0535badef22 (patch) | |
| tree | da51d33c76e4489af3e903ba92d20c3edd29e217 /techlibs/intel | |
| parent | d0d3ab8f676cd355d74cb7b7f71fc5bfca0719a2 (diff) | |
| parent | ef6548203cca239a98b00ea652a92fe3e20f97d7 (diff) | |
| download | yosys-3012e9eebc2950b996d17a018bb2e0535badef22.tar.gz yosys-3012e9eebc2950b996d17a018bb2e0535badef22.tar.bz2 yosys-3012e9eebc2950b996d17a018bb2e0535badef22.zip | |
Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor
Diffstat (limited to 'techlibs/intel')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index c8c690e45..a3d346407 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -71,7 +71,7 @@ struct SynthIntelPass : public ScriptPass { log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -210,7 +210,7 @@ struct SynthIntelPass : public ScriptPass { run("clean -purge"); run("setundef -undriven -zero"); if (retime || help_mode) - run("abc -markgroups -dff", "(only if -retime)"); + run("abc -markgroups -dff -D 1", "(only if -retime)"); } if (check_label("map_luts")) { |