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| author | Aman Goel <amangoel@umich.edu> | 2018-08-18 08:18:40 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-18 08:18:40 +0530 |
| commit | 61f002c908830d59e883d25668b731e7d12470d0 (patch) | |
| tree | 25174f7321f60e14ca6c144544f29971c40abe9b /techlibs/intel | |
| parent | 5dcb899e76a82c8aa84552a59f4a9f64394e7785 (diff) | |
| parent | e343f3e6d475984c21611474bffe7dcd8f599497 (diff) | |
| download | yosys-61f002c908830d59e883d25668b731e7d12470d0.tar.gz yosys-61f002c908830d59e883d25668b731e7d12470d0.tar.bz2 yosys-61f002c908830d59e883d25668b731e7d12470d0.zip | |
Merge pull request #3 from YosysHQ/master
Updates from official repo
Diffstat (limited to 'techlibs/intel')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index c51949bd4..d74f295ec 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct SynthIntelPass : public ScriptPass { SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass { string top_opt, family_opt, vout_file, blif_file; bool retime, flatten, nobram, noiopads; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; family_opt = "max10"; @@ -91,7 +91,7 @@ struct SynthIntelPass : public ScriptPass { noiopads = false; } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -156,7 +156,7 @@ struct SynthIntelPass : public ScriptPass { log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { @@ -255,7 +255,7 @@ struct SynthIntelPass : public ScriptPass { run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s", help_mode ? "<file-name>" : vout_file.c_str())); } - + if (check_label("vpr")) { if (!blif_file.empty() || help_mode) @@ -264,7 +264,7 @@ struct SynthIntelPass : public ScriptPass { run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str())); } } - } + } } SynthIntelPass; PRIVATE_NAMESPACE_END |