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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-02 12:48:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-10-02 12:48:04 +0200 |
| commit | a84a2d74c779b8023c0bbfc02fa4576d8c4cecca (patch) | |
| tree | 84e0a75011eb44e782772c64b64ef7b470257f89 /techlibs/intel | |
| parent | da347b9f7e8ce9738598931283ba98f8c98924cb (diff) | |
| download | yosys-a84a2d74c779b8023c0bbfc02fa4576d8c4cecca.tar.gz yosys-a84a2d74c779b8023c0bbfc02fa4576d8c4cecca.tar.bz2 yosys-a84a2d74c779b8023c0bbfc02fa4576d8c4cecca.zip | |
Fix btor back-end to use "state" instead of "input" for undef init bits
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/intel')
0 files changed, 0 insertions, 0 deletions