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| author | David Shah <dave@ds0.me> | 2019-07-25 08:19:07 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-25 08:19:07 +0100 |
| commit | ab607e896e9f5faff939b4395b01344a36e9fc1b (patch) | |
| tree | 8839dd684c71409ef542cb8573b4306477d6ed53 /techlibs/intel | |
| parent | 5939b5d636f80d4f9345f5b8d0247332d533b68c (diff) | |
| download | yosys-ab607e896e9f5faff939b4395b01344a36e9fc1b.tar.gz yosys-ab607e896e9f5faff939b4395b01344a36e9fc1b.tar.bz2 yosys-ab607e896e9f5faff939b4395b01344a36e9fc1b.zip | |
xilinx: Fix missing cell name underscore in cells_map.v
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/intel')
0 files changed, 0 insertions, 0 deletions