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| author | Clifford Wolf <clifford@clifford.at> | 2018-04-22 16:03:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-04-22 16:03:26 +0200 |
| commit | d9a2b43014696fe07c96c822b1009503d052ffc4 (patch) | |
| tree | bddec20ed04eb2fe1a9e2f4cff8844e1167c2363 /techlibs/intel | |
| parent | 81a457c4a68937f8edb4c48ca5a5de86b5c05769 (diff) | |
| download | yosys-d9a2b43014696fe07c96c822b1009503d052ffc4.tar.gz yosys-d9a2b43014696fe07c96c822b1009503d052ffc4.tar.bz2 yosys-d9a2b43014696fe07c96c822b1009503d052ffc4.zip | |
Add $dlatch support to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/intel')
0 files changed, 0 insertions, 0 deletions