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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-18 15:34:28 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-18 15:34:28 +0200 |
| commit | e66e8fb59d8443c8d55c1185d6b2ce889a35357d (patch) | |
| tree | 0bc17b70faef04b33bc736ce818ea4123921590f /techlibs/intel | |
| parent | 927f0caa9d70ccf3634b29d8558c78febcc9081c (diff) | |
| parent | 698ab9beeed7ee585117cc1e5f5126a9092942df (diff) | |
| download | yosys-e66e8fb59d8443c8d55c1185d6b2ce889a35357d.tar.gz yosys-e66e8fb59d8443c8d55c1185d6b2ce889a35357d.tar.bz2 yosys-e66e8fb59d8443c8d55c1185d6b2ce889a35357d.zip | |
Merge pull request #1184 from whitequark/synth-better-labels
synth_{ice40,ecp5}: more sensible pass label naming
Diffstat (limited to 'techlibs/intel')
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