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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-05-23 12:52:13 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-04 19:45:10 +0200 |
| commit | 83cde2d02ba06bbd4014858983ac324bf44cb6c6 (patch) | |
| tree | b999b0fc1a813b7683d85ba63b0cfd129e1d18b2 /techlibs/intel_alm/common/abc9_unmap.v | |
| parent | a9b61080a409d3ad2c8ff4a9bbef9ba1c9c1d194 (diff) | |
| download | yosys-83cde2d02ba06bbd4014858983ac324bf44cb6c6.tar.gz yosys-83cde2d02ba06bbd4014858983ac324bf44cb6c6.tar.bz2 yosys-83cde2d02ba06bbd4014858983ac324bf44cb6c6.zip | |
intel_alm: ABC9 sequential optimisations
Diffstat (limited to 'techlibs/intel_alm/common/abc9_unmap.v')
| -rw-r--r-- | techlibs/intel_alm/common/abc9_unmap.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/abc9_unmap.v b/techlibs/intel_alm/common/abc9_unmap.v new file mode 100644 index 000000000..0eda69560 --- /dev/null +++ b/techlibs/intel_alm/common/abc9_unmap.v @@ -0,0 +1,11 @@ +// After performing sequential synthesis, map the synchronous flops back to +// standard MISTRAL_FF flops. + +module MISTRAL_FF_SYNCONLY( + input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA, + output reg Q +); + +MISTRAL_FF _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ACLR(1'b1), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q)); + +endmodule |