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| author | Lofty <dan.ravensloft@gmail.com> | 2022-03-09 16:40:32 +0000 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2022-03-09 20:18:06 +0000 |
| commit | 9f7a55c99ff179e503397b5c9929de7ca97fd793 (patch) | |
| tree | 88d6e81cea45f30341a48a5cf25c7dc18c57ff9d /techlibs/intel_alm/common/bram_m10k_map.v | |
| parent | 4ccc2adbda523283997f273b0f182807ab07c0a9 (diff) | |
| download | yosys-9f7a55c99ff179e503397b5c9929de7ca97fd793.tar.gz yosys-9f7a55c99ff179e503397b5c9929de7ca97fd793.tar.bz2 yosys-9f7a55c99ff179e503397b5c9929de7ca97fd793.zip | |
intel_alm: M10K write-enable is negative-true
Diffstat (limited to 'techlibs/intel_alm/common/bram_m10k_map.v')
| -rw-r--r-- | techlibs/intel_alm/common/bram_m10k_map.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/bram_m10k_map.v b/techlibs/intel_alm/common/bram_m10k_map.v new file mode 100644 index 000000000..8f9d4a3b3 --- /dev/null +++ b/techlibs/intel_alm/common/bram_m10k_map.v @@ -0,0 +1,16 @@ +// Stub to invert M10K write-enable. + +module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + +parameter CFG_ABITS = 10; +parameter CFG_DBITS = 10; + +input CLK1; +input [CFG_ABITS-1:0] A1ADDR, B1ADDR; +input [CFG_DBITS-1:0] A1DATA; +input A1EN, B1EN; +output reg [CFG_DBITS-1:0] B1DATA; + +MISTRAL_M10K #(.CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN)); + +endmodule
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