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| author | Lofty <dan.ravensloft@gmail.com> | 2020-07-13 14:08:52 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-13 18:05:38 +0200 |
| commit | a3a90f6377f251d3b6c5898eb1543f8832493bb8 (patch) | |
| tree | 675edf92b662112079a0b3384d406b8f5526a3de /techlibs/intel_alm/common/bram_m10k_map.v | |
| parent | 38b814b525d9d3abbfea060a8156b64b15aa7cf3 (diff) | |
| download | yosys-a3a90f6377f251d3b6c5898eb1543f8832493bb8.tar.gz yosys-a3a90f6377f251d3b6c5898eb1543f8832493bb8.tar.bz2 yosys-a3a90f6377f251d3b6c5898eb1543f8832493bb8.zip | |
Revert "intel_alm: direct M10K instantiation"
This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
Diffstat (limited to 'techlibs/intel_alm/common/bram_m10k_map.v')
| -rw-r--r-- | techlibs/intel_alm/common/bram_m10k_map.v | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/bram_m10k_map.v b/techlibs/intel_alm/common/bram_m10k_map.v new file mode 100644 index 000000000..061463c3e --- /dev/null +++ b/techlibs/intel_alm/common/bram_m10k_map.v @@ -0,0 +1,31 @@ +module __MISTRAL_M10K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+
+parameter CFG_ABITS = 10;
+parameter CFG_DBITS = 10;
+parameter CFG_ENABLE_A = 1;
+parameter CFG_ENABLE_B = 1;
+
+input CLK1;
+input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
+input [CFG_DBITS-1:0] A1DATA;
+output [CFG_DBITS-1:0] B1DATA;
+input [CFG_ENABLE_A-1:0] A1EN, B1EN;
+
+altsyncram #(
+ .operation_mode("dual_port"),
+ .ram_block_type("m10k"),
+ .widthad_a(CFG_ABITS),
+ .width_a(CFG_DBITS),
+ .widthad_b(CFG_ABITS),
+ .width_b(CFG_DBITS),
+) _TECHMAP_REPLACE_ (
+ .address_a(A1ADDR),
+ .data_a(A1DATA),
+ .wren_a(A1EN),
+ .address_b(B1ADDR),
+ .q_b(B1DATA),
+ .clock0(CLK1),
+ .clock1(CLK1)
+);
+
+endmodule
|