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| author | whitequark <whitequark@whitequark.org> | 2020-04-14 14:37:48 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-14 14:37:48 +0000 |
| commit | d8f2a1fda0876f78a85cb5e1674b6ada8a8726f2 (patch) | |
| tree | af30b7ffd3a2dea84f89c13adcd68e2eb1e645bd /techlibs/intel_alm/common/bram_m20k_map.v | |
| parent | 7025881a5e8c4feb077d296f996683094e2a313a (diff) | |
| parent | 0d0bf9c4a2acd70418670518bf641f7628c92165 (diff) | |
| download | yosys-d8f2a1fda0876f78a85cb5e1674b6ada8a8726f2.tar.gz yosys-d8f2a1fda0876f78a85cb5e1674b6ada8a8726f2.tar.bz2 yosys-d8f2a1fda0876f78a85cb5e1674b6ada8a8726f2.zip | |
Merge pull request #1922 from whitequark/write_cxxrtl-disconnected-outputs
write_cxxrtl: ignore disconnected module ports
Diffstat (limited to 'techlibs/intel_alm/common/bram_m20k_map.v')
0 files changed, 0 insertions, 0 deletions