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| author | Lofty <dan.ravensloft@gmail.com> | 2021-11-24 21:20:40 +0000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-25 17:20:36 +0100 |
| commit | a31c8a82be4ec98dbe58ce7efdde3a372b9767e0 (patch) | |
| tree | fb291eb084201f1f1669e36cb6533b9adb43d101 /techlibs/intel_alm/common/dff_sim.v | |
| parent | 77327b2544a30b15e8efc79e1f62661ff25d306c (diff) | |
| download | yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.tar.gz yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.tar.bz2 yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.zip | |
intel_alm: preliminary Arria V support
Diffstat (limited to 'techlibs/intel_alm/common/dff_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/dff_sim.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/dff_sim.v b/techlibs/intel_alm/common/dff_sim.v index 6bee994be..8d58bf614 100644 --- a/techlibs/intel_alm/common/dff_sim.v +++ b/techlibs/intel_alm/common/dff_sim.v @@ -77,6 +77,21 @@ specify if (ACLR === 1'b0) (ACLR => Q) = 282; endspecify `endif +`ifdef arriav +specify + if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 470; + if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 633; + if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 439; + + $setup(DATAIN, posedge CLK, /* -170 */ 0); + $setup(ENA, posedge CLK, /* -170 */ 0); + $setup(SCLR, posedge CLK, /* -170 */ 0); + $setup(SLOAD, posedge CLK, /* -170 */ 0); + $setup(SDATA, posedge CLK, /* -170 */ 0); + + if (ACLR === 1'b0) (ACLR => Q) = 215; +endspecify +`endif `ifdef cyclone10gx specify // TODO (long-term): investigate these numbers. |