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| author | Miodrag Milanović <mmicko@gmail.com> | 2020-07-17 14:39:31 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-17 14:39:31 +0200 |
| commit | 10bc0967e270cede75e38264b48621a07387d8e3 (patch) | |
| tree | 6827e7249968cd725fe87f1f7146c89de0c97122 /techlibs/intel_alm/common/dsp_sim.v | |
| parent | 9a5d6e178976a43ff3f875ea8630f94b6abb64c0 (diff) | |
| parent | a4f7777e9dd916d5dfb7d76e899916805e0ad334 (diff) | |
| download | yosys-10bc0967e270cede75e38264b48621a07387d8e3.tar.gz yosys-10bc0967e270cede75e38264b48621a07387d8e3.tar.bz2 yosys-10bc0967e270cede75e38264b48621a07387d8e3.zip | |
Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix
anlogic: Fix FF mapping.
Diffstat (limited to 'techlibs/intel_alm/common/dsp_sim.v')
0 files changed, 0 insertions, 0 deletions