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| author | Andy Knowles <andy.knowles@gmail.com> | 2020-08-12 11:32:57 +0200 |
|---|---|---|
| committer | Andy Knowles <andy.knowles@gmail.com> | 2020-08-12 11:32:57 +0200 |
| commit | 1227c3681be8e6365e91e77b06dcbe58ff6c7593 (patch) | |
| tree | 5c71baa228456d2a286d1788b8261e609801de11 /techlibs/intel_alm/common/dsp_sim.v | |
| parent | 04f6158bf2ce9a95970f1be435351786f59bed92 (diff) | |
| download | yosys-1227c3681be8e6365e91e77b06dcbe58ff6c7593.tar.gz yosys-1227c3681be8e6365e91e77b06dcbe58ff6c7593.tar.bz2 yosys-1227c3681be8e6365e91e77b06dcbe58ff6c7593.zip | |
cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False
Diffstat (limited to 'techlibs/intel_alm/common/dsp_sim.v')
0 files changed, 0 insertions, 0 deletions