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| author | Lofty <dan.ravensloft@gmail.com> | 2021-11-24 21:20:40 +0000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-25 17:20:36 +0100 |
| commit | a31c8a82be4ec98dbe58ce7efdde3a372b9767e0 (patch) | |
| tree | fb291eb084201f1f1669e36cb6533b9adb43d101 /techlibs/intel_alm/common/dsp_sim.v | |
| parent | 77327b2544a30b15e8efc79e1f62661ff25d306c (diff) | |
| download | yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.tar.gz yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.tar.bz2 yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.zip | |
intel_alm: preliminary Arria V support
Diffstat (limited to 'techlibs/intel_alm/common/dsp_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/dsp_sim.v | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v index bdb6d18d5..3d4b5590b 100644 --- a/techlibs/intel_alm/common/dsp_sim.v +++ b/techlibs/intel_alm/common/dsp_sim.v @@ -1,14 +1,31 @@ +`default_nettype none + (* abc9_box *) module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y); parameter A_SIGNED = 1; parameter B_SIGNED = 1; +`ifdef cyclonev +specify + (A *> Y) = 3732; + (B *> Y) = 3928; +endspecify +`endif +`ifdef arriav +// NOTE: Arria V appears to have only one set of timings for all DSP modes... +specify + (A *> Y) = 1895; + (B *> Y) = 2053; +endspecify +`endif +`ifdef cyclone10gx // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify (A *> Y) = 3732; (B *> Y) = 3928; endspecify +`endif wire [53:0] A_, B_; @@ -32,11 +49,26 @@ module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y); parameter A_SIGNED = 1; parameter B_SIGNED = 1; +`ifdef cyclonev +specify + (A *> Y) = 3180; + (B *> Y) = 3982; +endspecify +`endif +`ifdef arriav +// NOTE: Arria V appears to have only one set of timings for all DSP modes... +specify + (A *> Y) = 1895; + (B *> Y) = 2053; +endspecify +`endif +`ifdef cyclone10gx // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify (A *> Y) = 3180; (B *> Y) = 3982; endspecify +`endif wire [35:0] A_, B_; @@ -60,11 +92,26 @@ module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y); parameter A_SIGNED = 1; parameter B_SIGNED = 1; +`ifdef cyclonev +specify + (A *> Y) = 2818; + (B *> Y) = 3051; +endspecify +`endif +`ifdef arriav +// NOTE: Arria V appears to have only one set of timings for all DSP modes... +specify + (A *> Y) = 1895; + (B *> Y) = 2053; +endspecify +`endif +`ifdef cyclone10gx // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify (A *> Y) = 2818; (B *> Y) = 3051; endspecify +`endif wire [17:0] A_, B_; |