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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-04-25 17:25:59 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 05:39:20 +0200 |
| commit | b004f0901873962ba4a6fd3e12c7bc0cc1e04032 (patch) | |
| tree | 16d1bceb58a8b58690b5ba849173bfeef015bd4e /techlibs/intel_alm/common/dsp_sim.v | |
| parent | 01772dec8c13fb331df439319f4619b6292d6409 (diff) | |
| download | yosys-b004f0901873962ba4a6fd3e12c7bc0cc1e04032.tar.gz yosys-b004f0901873962ba4a6fd3e12c7bc0cc1e04032.tar.bz2 yosys-b004f0901873962ba4a6fd3e12c7bc0cc1e04032.zip | |
intel_alm: DSP inference
Diffstat (limited to 'techlibs/intel_alm/common/dsp_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/dsp_sim.v | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v new file mode 100644 index 000000000..5dc4c02de --- /dev/null +++ b/techlibs/intel_alm/common/dsp_sim.v @@ -0,0 +1,35 @@ +(* abc9_box *) +module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y); + +specify + (A *> Y) = 4057; + (B *> Y) = 4057; +endspecify + +assign Y = $signed(A) * $signed(B); + +endmodule + +(* abc9_box *) +module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y); + +specify + (A *> Y) = 4057; + (B *> Y) = 4057; +endspecify + +assign Y = $signed(A) * $signed(B); + +endmodule + +(* abc9_box *) +module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y); + +specify + (A *> Y) = 4057; + (B *> Y) = 4057; +endspecify + +assign Y = $signed(A) * $signed(B); + +endmodule |