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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-04-16 12:24:04 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-07 21:03:13 +0200 |
| commit | 5b779f7f4ef0bf2c4ad3a412da24fad30b078626 (patch) | |
| tree | cb0fcd56575efe8a846fbd6a2888aee80998f644 /techlibs/intel_alm/common/lutram_mlab.txt | |
| parent | 06104249406972de01d0360df63a32cafcdf2ec5 (diff) | |
| download | yosys-5b779f7f4ef0bf2c4ad3a412da24fad30b078626.tar.gz yosys-5b779f7f4ef0bf2c4ad3a412da24fad30b078626.tar.bz2 yosys-5b779f7f4ef0bf2c4ad3a412da24fad30b078626.zip | |
intel_alm: direct LUTRAM cell instantiation
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
Diffstat (limited to 'techlibs/intel_alm/common/lutram_mlab.txt')
| -rw-r--r-- | techlibs/intel_alm/common/lutram_mlab.txt | 38 |
1 files changed, 18 insertions, 20 deletions
diff --git a/techlibs/intel_alm/common/lutram_mlab.txt b/techlibs/intel_alm/common/lutram_mlab.txt index 1d6174d85..3cc69399d 100644 --- a/techlibs/intel_alm/common/lutram_mlab.txt +++ b/techlibs/intel_alm/common/lutram_mlab.txt @@ -1,20 +1,18 @@ -bram __MISTRAL_MLAB
- init 0 # TODO: Re-enable when I figure out how LUTRAM init works
- abits 5
- dbits 16 @D32x16
- dbits 18 @D32x18
- dbits 20 @D32x20
- groups 2
- ports 1 1
- wrmode 1 0
- # read enable
- enable 1 0
- transp 1 0
- clocks 1 2
- clkpol 1 1
-endbram
-
-match __MISTRAL_MLAB
- min efficiency 5
- make_outreg
-endmatch
+bram MISTRAL_MLAB + init 0 # TODO: Re-enable when Yosys remembers the original filename. + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 1 0 + # write enable + enable 1 0 + transp 0 0 + clocks 1 0 + clkpol 1 1 +endbram + +match MISTRAL_MLAB + min efficiency 5 + make_outreg +endmatch
\ No newline at end of file |