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| author | clairexen <claire@symbioticeda.com> | 2020-07-23 18:21:20 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-23 18:21:20 +0200 |
| commit | 02583ad50453ec332c4745d97eca67d720f1442e (patch) | |
| tree | ec9e4915826e3d3c58a38f539f9caf71f7ae98f9 /techlibs/intel_alm/common/mem_sim.v | |
| parent | 819f1d8c20e07da66122292b90603867b78ff2d2 (diff) | |
| parent | 4d9d90079c6e069fcba7ce04e8005285f4f237fe (diff) | |
| download | yosys-02583ad50453ec332c4745d97eca67d720f1442e.tar.gz yosys-02583ad50453ec332c4745d97eca67d720f1442e.tar.bz2 yosys-02583ad50453ec332c4745d97eca67d720f1442e.zip | |
Merge pull request #2294 from Ravenslofty/intel_alm_timings
intel_alm: add additional ABC9 timings
Diffstat (limited to 'techlibs/intel_alm/common/mem_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/mem_sim.v | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v index f6f9ecb02..b0e1763db 100644 --- a/techlibs/intel_alm/common/mem_sim.v +++ b/techlibs/intel_alm/common/mem_sim.v @@ -54,12 +54,17 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1 reg [31:0] mem = 32'b0; -// TODO +// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V specify - $setup(A1ADDR, posedge CLK1, 0); - $setup(A1DATA, posedge CLK1, 0); + $setup(A1ADDR, posedge CLK1, 86); + $setup(A1DATA, posedge CLK1, 86); + $setup(A1EN, posedge CLK1, 86); - (B1ADDR *> B1DATA) = 0; + (B1ADDR[0] => B1DATA) = 487; + (B1ADDR[1] => B1DATA) = 475; + (B1ADDR[2] => B1DATA) = 382; + (B1ADDR[3] => B1DATA) = 284; + (B1ADDR[4] => B1DATA) = 96; endspecify always @(posedge CLK1) |