diff options
| author | Lofty <dan.ravensloft@gmail.com> | 2022-03-09 16:40:32 +0000 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2022-03-09 20:18:06 +0000 |
| commit | 9f7a55c99ff179e503397b5c9929de7ca97fd793 (patch) | |
| tree | 88d6e81cea45f30341a48a5cf25c7dc18c57ff9d /techlibs/intel_alm/common/mem_sim.v | |
| parent | 4ccc2adbda523283997f273b0f182807ab07c0a9 (diff) | |
| download | yosys-9f7a55c99ff179e503397b5c9929de7ca97fd793.tar.gz yosys-9f7a55c99ff179e503397b5c9929de7ca97fd793.tar.bz2 yosys-9f7a55c99ff179e503397b5c9929de7ca97fd793.zip | |
intel_alm: M10K write-enable is negative-true
Diffstat (limited to 'techlibs/intel_alm/common/mem_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/mem_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v index 370e17f27..c9ba8c7f1 100644 --- a/techlibs/intel_alm/common/mem_sim.v +++ b/techlibs/intel_alm/common/mem_sim.v @@ -145,7 +145,7 @@ endspecify `endif always @(posedge CLK1) begin - if (A1EN) + if (!A1EN) mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA; if (B1EN) |