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| author | Claire Xen <claire@clairexen.net> | 2022-02-11 16:03:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-11 16:03:12 +0100 |
| commit | 49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch) | |
| tree | d0f20b8def36e551c6735d4fc6033aaa2633fe80 /techlibs/intel_alm/common/misc_sim.v | |
| parent | 90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff) | |
| parent | e0165188669fcef2c5784c9916683889a2164e5d (diff) | |
| download | yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.gz yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.bz2 yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.zip | |
Merge branch 'master' into clk2ff-better-names
Diffstat (limited to 'techlibs/intel_alm/common/misc_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/misc_sim.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/misc_sim.v b/techlibs/intel_alm/common/misc_sim.v new file mode 100644 index 000000000..b1f970a21 --- /dev/null +++ b/techlibs/intel_alm/common/misc_sim.v @@ -0,0 +1,21 @@ +module MISTRAL_IB((* iopad_external_pin *) input PAD, output O); + assign O = PAD; +endmodule + +module MISTRAL_OB((* iopad_external_pin *) output PAD, input I); + assign PAD = I; +endmodule + +module MISTRAL_IO((* iopad_external_pin *) inout PAD, input I, input OE, output O); + assign PAD = OE ? I : 1'bz; + assign O = PAD; +endmodule + +// Eventually, we should support clock enables and model them here too. +// For now, CLKENA is used as a basic entry point to global routing. +module MISTRAL_CLKBUF ( + input A, + (* clkbuf_driver *) output Q +); + assign Q = A; +endmodule
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