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| author | whitequark <whitequark@whitequark.org> | 2020-04-14 12:34:35 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-14 12:36:20 +0000 |
| commit | 0d0bf9c4a2acd70418670518bf641f7628c92165 (patch) | |
| tree | 8e1b8e2265368f8dedcb3aad577680b6f00078d8 /techlibs/intel_alm/common | |
| parent | f44b287f8e36684607447beb05556f1a5a34d625 (diff) | |
| download | yosys-0d0bf9c4a2acd70418670518bf641f7628c92165.tar.gz yosys-0d0bf9c4a2acd70418670518bf641f7628c92165.tar.bz2 yosys-0d0bf9c4a2acd70418670518bf641f7628c92165.zip | |
write_cxxrtl: ignore disconnected module ports.
E.g. port `q` in `submod x(.p(p), .q());`.
Fixes #1920.
Diffstat (limited to 'techlibs/intel_alm/common')
0 files changed, 0 insertions, 0 deletions