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authorgatecat <gatecat@ds0.me>2021-05-15 14:23:22 +0100
committergatecat <gatecat@ds0.me>2021-05-15 22:37:06 +0100
commit5dba138c87762d4b5bb7b9348da372a92fab1cc0 (patch)
tree764f5d928b3e06b6a4884d5d1b14e4533003d18e /techlibs/intel_alm/cyclonev/cells_sim.v
parent3421979f00664443c77b0899d34438f979b4c51c (diff)
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intel_alm: Add IO buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'techlibs/intel_alm/cyclonev/cells_sim.v')
-rw-r--r--techlibs/intel_alm/cyclonev/cells_sim.v28
1 files changed, 23 insertions, 5 deletions
diff --git a/techlibs/intel_alm/cyclonev/cells_sim.v b/techlibs/intel_alm/cyclonev/cells_sim.v
index 9b2a10e72..d0a9d9179 100644
--- a/techlibs/intel_alm/cyclonev/cells_sim.v
+++ b/techlibs/intel_alm/cyclonev/cells_sim.v
@@ -26,16 +26,34 @@ endmodule // GND
/* Altera Cyclone V devices Input Buffer Primitive */
module cyclonev_io_ibuf
- (output o, input i, input ibar);
- assign ibar = ibar;
+ (output o,
+ (* iopad_external_pin *) input i,
+ (* iopad_external_pin *) input ibar,
+ input dynamicterminationcontrol);
+
+ parameter differential_mode = "false";
+ parameter bus_hold = "false";
+ parameter simulate_z_as = "Z";
+ parameter lpm_type = "cyclonev_io_ibuf";
+
assign o = i;
endmodule // cyclonev_io_ibuf
/* Altera Cyclone V devices Output Buffer Primitive */
module cyclonev_io_obuf
- (output o, input i, input oe);
- assign o = i;
- assign oe = oe;
+ ((* iopad_external_pin *) output o,
+ input i, oe, dynamicterminationcontrol,
+ input [15:0] seriesterminationcontrol, parallelterminationcontrol,
+ input devoe,
+ (* iopad_external_pin *) output obar);
+
+ parameter open_drain_output = "false";
+ parameter bus_hold = "false";
+ parameter shift_series_termination_control = "false";
+ parameter sim_dynamic_termination_control_is_connected = "false";
+ parameter lpm_type = "cyclonev_io_obuf";
+
+ assign o = oe ? i : 1'bz;
endmodule // cyclonev_io_obuf
/* Altera Cyclone V LUT Primitive */