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| author | Peter Crozier <peter@crozier.com> | 2020-06-03 17:19:28 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-03 17:19:28 +0100 |
| commit | 0d3f7ea011288e1a1fadd4ae27f1e8a57d729053 (patch) | |
| tree | 07bde0d9f492233728070234aed2abd45fbd464d /techlibs/intel_alm/synth_intel_alm.cc | |
| parent | 17f050d3c6b8934141c42f96a3418de67a687b2c (diff) | |
| parent | 46ed0db2ec883a4ce330c81f321511e36e35c0b3 (diff) | |
| download | yosys-0d3f7ea011288e1a1fadd4ae27f1e8a57d729053.tar.gz yosys-0d3f7ea011288e1a1fadd4ae27f1e8a57d729053.tar.bz2 yosys-0d3f7ea011288e1a1fadd4ae27f1e8a57d729053.zip | |
Merge branch 'master' into struct
Diffstat (limited to 'techlibs/intel_alm/synth_intel_alm.cc')
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index bf9e746b8..0f844961e 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_luts")) { - run("read_verilog -icells -specify -lib +/abc9_model.v"); run("abc9 -maxlut 6 -W 200"); run("techmap -map +/intel_alm/common/alm_map.v"); run("opt -fast"); |