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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-18 08:06:50 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-18 08:06:50 -0700 |
| commit | 2d573a0ff680eb9f38358943fbf134f765ba1451 (patch) | |
| tree | f68589c127fcb0972636699b888252972ed63385 /techlibs/intel_alm/synth_intel_alm.cc | |
| parent | fa8cb3e35da68ceb55a9147bc1faacf68ad8bbfa (diff) | |
| parent | 67fc0c3698693f049e805211c49d6219f17d7c7d (diff) | |
| download | yosys-2d573a0ff680eb9f38358943fbf134f765ba1451.tar.gz yosys-2d573a0ff680eb9f38358943fbf134f765ba1451.tar.bz2 yosys-2d573a0ff680eb9f38358943fbf134f765ba1451.zip | |
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
Diffstat (limited to 'techlibs/intel_alm/synth_intel_alm.cc')
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index bf9e746b8..0f844961e 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_luts")) { - run("read_verilog -icells -specify -lib +/abc9_model.v"); run("abc9 -maxlut 6 -W 200"); run("techmap -map +/intel_alm/common/alm_map.v"); run("opt -fast"); |