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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-26 08:38:11 -0700 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-04 19:45:10 +0200 |
| commit | 2bdced0d68f3f3a1ea43741c49435d482698a8ca (patch) | |
| tree | 4aa15a07f6c32da454466d5f89ca653b6f2d5d6c /techlibs/intel_alm | |
| parent | 0ba79feb6f0b77120f113dec268908bf25306581 (diff) | |
| download | yosys-2bdced0d68f3f3a1ea43741c49435d482698a8ca.tar.gz yosys-2bdced0d68f3f3a1ea43741c49435d482698a8ca.tar.bz2 yosys-2bdced0d68f3f3a1ea43741c49435d482698a8ca.zip | |
intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
Diffstat (limited to 'techlibs/intel_alm')
| -rw-r--r-- | techlibs/intel_alm/common/abc9_model.v | 47 | ||||
| -rw-r--r-- | techlibs/intel_alm/common/dff_sim.v | 2 |
2 files changed, 2 insertions, 47 deletions
diff --git a/techlibs/intel_alm/common/abc9_model.v b/techlibs/intel_alm/common/abc9_model.v index 8ad52e13a..8f06d3835 100644 --- a/techlibs/intel_alm/common/abc9_model.v +++ b/techlibs/intel_alm/common/abc9_model.v @@ -1,21 +1,3 @@ -`ifdef cyclonev -`define SYNCPATH 262 -`define SYNCSETUP 522 -`define COMBPATH 0 -`endif -`ifdef cyclone10gx -`define SYNCPATH 219 -`define SYNCSETUP 268 -`define COMBPATH 0 -`endif - -// fallback for when a family isn't detected (e.g. when techmapping for equivalence) -`ifndef SYNCPATH -`define SYNCPATH 0 -`define SYNCSETUP 0 -`define COMBPATH 0 -`endif - // This is a purely-synchronous flop, that ABC9 can use for sequential synthesis. (* abc9_flop, lib_whitebox *) module $__MISTRAL_FF_SYNCONLY ( @@ -23,33 +5,6 @@ module $__MISTRAL_FF_SYNCONLY ( output reg Q ); -specify - if (ENA) (posedge CLK => (Q : DATAIN)) = `SYNCPATH; - if (ENA) (posedge CLK => (Q : SCLR)) = `SYNCPATH; - if (ENA) (posedge CLK => (Q : SLOAD)) = `SYNCPATH; - if (ENA) (posedge CLK => (Q : SDATA)) = `SYNCPATH; - - $setup(DATAIN, posedge CLK, `SYNCSETUP); - $setup(ENA, posedge CLK, `SYNCSETUP); - $setup(SCLR, posedge CLK, `SYNCSETUP); - $setup(SLOAD, posedge CLK, `SYNCSETUP); - $setup(SDATA, posedge CLK, `SYNCSETUP); -endspecify - -initial begin - // Altera flops initialise to zero. - Q = 0; -end - -always @(posedge CLK) begin - // Clock-enable - if (ENA) begin - // Synchronous clear - if (SCLR) Q <= 0; - // Synchronous load - else if (SLOAD) Q <= SDATA; - else Q <= DATAIN; - end -end +MISTRAL_FF ff (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .ACLR(1'b1), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q)); endmodule diff --git a/techlibs/intel_alm/common/dff_sim.v b/techlibs/intel_alm/common/dff_sim.v index 94aa37fb5..38e3d6618 100644 --- a/techlibs/intel_alm/common/dff_sim.v +++ b/techlibs/intel_alm/common/dff_sim.v @@ -90,7 +90,7 @@ specify $setup(SLOAD, posedge CLK, `SYNCSETUP); $setup(SDATA, posedge CLK, `SYNCSETUP); - (ACLR => Q) = `COMBPATH; + if (!ACLR) (ACLR => Q) = `COMBPATH; endspecify initial begin |