aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/intel_alm
diff options
context:
space:
mode:
authorKrystalDelusion <krystinedawn@yosyshq.com>2022-08-24 10:28:27 +1200
committerKrystalDelusion <krystinedawn@yosyshq.com>2022-08-24 10:40:57 +1200
commit9465b2af95a146f514fc1e0b2d31bc3d9a233fb7 (patch)
tree59001b194c2f573674c37352733427a3ec28a1c1 /techlibs/intel_alm
parent029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff)
downloadyosys-9465b2af95a146f514fc1e0b2d31bc3d9a233fb7.tar.gz
yosys-9465b2af95a146f514fc1e0b2d31bc3d9a233fb7.tar.bz2
yosys-9465b2af95a146f514fc1e0b2d31bc3d9a233fb7.zip
Fitting help messages to 80 character width
Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
Diffstat (limited to 'techlibs/intel_alm')
-rw-r--r--techlibs/intel_alm/synth_intel_alm.cc13
1 files changed, 8 insertions, 5 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 43d3592d5..c33eb43bf 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -43,21 +43,24 @@ struct SynthIntelALMPass : public ScriptPass {
log(" -family <family>\n");
log(" target one of:\n");
log(" \"cyclonev\" - Cyclone V (default)\n");
- log(" \"arriav\" - Arria V (non-GZ)");
+ log(" \"arriav\" - Arria V (non-GZ)\n");
log(" \"cyclone10gx\" - Cyclone 10GX\n");
log("\n");
log(" -vqm <file>\n");
- log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
- log(" output file is omitted if this parameter is not specified. Implies -quartus.\n");
+ log(" write the design to the specified Verilog Quartus Mapping File. Writing\n");
+ log(" of an output file is omitted if this parameter is not specified. Implies\n");
+ log(" -quartus.\n");
log("\n");
log(" -noflatten\n");
- log(" do not flatten design before synthesis; useful for per-module area statistics\n");
+ log(" do not flatten design before synthesis; useful for per-module area\n");
+ log(" statistics\n");
log("\n");
log(" -quartus\n");
log(" output a netlist using Quartus cells instead of MISTRAL_* cells\n");
log("\n");
log(" -dff\n");
- log(" pass DFFs to ABC to perform sequential logic optimisations (EXPERIMENTAL)\n");
+ log(" pass DFFs to ABC to perform sequential logic optimisations\n");
+ log(" (EXPERIMENTAL)\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");