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| author | William D. Jones <thor0505@comcast.net> | 2021-01-29 18:14:13 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | 8348c45e4f679b44b238c0f205e2e3815c909c38 (patch) | |
| tree | a711146a578afa58ace19f3e79b146b5f542d872 /techlibs/machxo2/cells_sim.v | |
| parent | 120404bfda90578a014ba702d457eb85ae3711d7 (diff) | |
| download | yosys-8348c45e4f679b44b238c0f205e2e3815c909c38.tar.gz yosys-8348c45e4f679b44b238c0f205e2e3815c909c38.tar.bz2 yosys-8348c45e4f679b44b238c0f205e2e3815c909c38.zip | |
machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.
Diffstat (limited to 'techlibs/machxo2/cells_sim.v')
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 3dd41334e..4e2a1bb6c 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -162,16 +162,16 @@ module FACADE_IO #( parameter DIR = "INPUT" ) ( inout PAD, - input I, EN, + input I, T, output O ); generate if (DIR == "INPUT") begin assign O = PAD; end else if (DIR == "OUTPUT") begin - assign PAD = EN ? I : 1'bz; + assign PAD = T ? I : 1'bz; end else if (DIR == "BIDIR") begin - assign PAD = EN ? I : 1'bz; + assign PAD = T ? I : 1'bz; assign O = PAD; end else begin ERROR_UNKNOWN_IO_MODE error(); |