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| author | William D. Jones <thor0505@comcast.net> | 2020-12-12 18:09:52 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | 3674eb34d4e3719798a274a251150a7687064422 (patch) | |
| tree | cd0b6379d0ff5d87522e0c1ba86b0d64bc072302 /techlibs/machxo2/synth_machxo2.cc | |
| parent | 124780ecd9a74e9477313975b5e06e3fdd902573 (diff) | |
| download | yosys-3674eb34d4e3719798a274a251150a7687064422.tar.gz yosys-3674eb34d4e3719798a274a251150a7687064422.tar.bz2 yosys-3674eb34d4e3719798a274a251150a7687064422.zip | |
machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells.
Diffstat (limited to 'techlibs/machxo2/synth_machxo2.cc')
| -rw-r--r-- | techlibs/machxo2/synth_machxo2.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/machxo2/synth_machxo2.cc b/techlibs/machxo2/synth_machxo2.cc index c9ab23426..ea9b2a0e8 100644 --- a/techlibs/machxo2/synth_machxo2.cc +++ b/techlibs/machxo2/synth_machxo2.cc @@ -154,7 +154,7 @@ struct SynthMachXO2Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib +/machxo2/cells_sim.v"); + run("read_verilog -lib -icells +/machxo2/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); } @@ -184,7 +184,11 @@ struct SynthMachXO2Pass : public ScriptPass if (check_label("map_ios")) { if (!noiopad || help_mode) + { run("iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD OE:I:O -tinoutpad $__FACADE_TINOUTPAD OE:O:I:B A:top", "(skip if '-noiopad')"); + run("attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B]", "(skip if '-noiopad')"); + run("attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]", "(skip if '-noiopad')"); + } } if (check_label("map_ffs")) |