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| author | Lofty <dan.ravensloft@gmail.com> | 2021-03-17 02:34:30 +0000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-18 13:28:16 +0100 |
| commit | f4298b057ae0939b83283c8c7431097e71a32b62 (patch) | |
| tree | eedd3de21b55af0c2952fd8e730fb165c89fa8a3 /techlibs/quicklogic/pp3_latches_map.v | |
| parent | 8740fdf1d799fd8a3196bac28fe4e418e74f2acc (diff) | |
| download | yosys-f4298b057ae0939b83283c8c7431097e71a32b62.tar.gz yosys-f4298b057ae0939b83283c8c7431097e71a32b62.tar.bz2 yosys-f4298b057ae0939b83283c8c7431097e71a32b62.zip | |
quicklogic: PolarPro 3 support
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
Diffstat (limited to 'techlibs/quicklogic/pp3_latches_map.v')
| -rw-r--r-- | techlibs/quicklogic/pp3_latches_map.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/quicklogic/pp3_latches_map.v b/techlibs/quicklogic/pp3_latches_map.v new file mode 100644 index 000000000..240a3fb4e --- /dev/null +++ b/techlibs/quicklogic/pp3_latches_map.v @@ -0,0 +1,11 @@ +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule + +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule |