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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
| commit | c06c062469a6f5ea16116a5ed3bc4a45b6e818a2 (patch) | |
| tree | ea54f3510f2e85771422718385028b0864696cba /techlibs/sf2/cells_sim.v | |
| parent | 8ddec5d882c6834cb6b3415e05a2a88d416cabff (diff) | |
| parent | e45f62b0c56717a23099425f078d1e56212aa632 (diff) | |
| download | yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.gz yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.bz2 yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
Diffstat (limited to 'techlibs/sf2/cells_sim.v')
| -rw-r--r-- | techlibs/sf2/cells_sim.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v index b03b2c750..f967068af 100644 --- a/techlibs/sf2/cells_sim.v +++ b/techlibs/sf2/cells_sim.v @@ -73,3 +73,24 @@ module CFG4 ( parameter [15:0] INIT = 16'h0; assign Y = INIT >> {D, C, B, A}; endmodule + +module CLKBUF ( + input PAD, + output Y +); + assign Y = PAD; +endmodule + +module INBUF ( + input PAD, + output Y +); + assign Y = PAD; +endmodule + +module OUTBUF ( + input D, + output PAD +); + assign PAD = D; +endmodule |