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| author | Tristan Gingold <tristan.gingold@cern.ch> | 2021-11-24 17:08:47 +0100 |
|---|---|---|
| committer | Tristan Gingold <tristan.gingold@cern.ch> | 2022-08-31 08:40:44 +0200 |
| commit | c25f3ff3df8ec0c6979af6fa938716e461c8261b (patch) | |
| tree | 18097531ee75e4c261b8973c45ec73092b118151 /techlibs/sf2/cells_sim.v | |
| parent | 13ccdd032d5a17f7190014b9964b3eda644dca55 (diff) | |
| download | yosys-c25f3ff3df8ec0c6979af6fa938716e461c8261b.tar.gz yosys-c25f3ff3df8ec0c6979af6fa938716e461c8261b.tar.bz2 yosys-c25f3ff3df8ec0c6979af6fa938716e461c8261b.zip | |
sf2: suport $alu gate and ARI1 implementation
Diffstat (limited to 'techlibs/sf2/cells_sim.v')
| -rw-r--r-- | techlibs/sf2/cells_sim.v | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v index c0b50382f..02335404b 100644 --- a/techlibs/sf2/cells_sim.v +++ b/techlibs/sf2/cells_sim.v @@ -152,7 +152,22 @@ module SLE ( assign Q = LAT ? q_latch : q_ff; endmodule -// module AR1 +module ARI1 ( + input A, B, C, D, FCI, + output Y, S, FCO +); + parameter [19:0] INIT = 20'h0; + wire [2:0] Fsel = {D, C, B}; + wire F0 = INIT[Fsel]; + wire F1 = INIT[8 + Fsel]; + wire Yout = A ? F1 : F0; + assign Y = Yout; + wire S = FCI ^ Yout; + wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17]; + wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0); + assign FCO = P ? FCI : G; +endmodule + // module FCEND_BUFF // module FCINIT_BUFF // module FLASH_FREEZE |