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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-08-31 09:30:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-31 09:30:09 +0200 |
| commit | d8a383b5553d3a3068659e632cf8daf01ac384ee (patch) | |
| tree | 95ce798dbe7a947a9ec454b8c1f12379db85acdf /techlibs/sf2/tests/test_arith.ys | |
| parent | d829d7fe00b340b2d837bdadf6d446ee10c2d4aa (diff) | |
| parent | 1e0e3bd48e2f90399fe59ea3607ce68163891284 (diff) | |
| download | yosys-d8a383b5553d3a3068659e632cf8daf01ac384ee.tar.gz yosys-d8a383b5553d3a3068659e632cf8daf01ac384ee.tar.bz2 yosys-d8a383b5553d3a3068659e632cf8daf01ac384ee.zip | |
Merge pull request #3087 from tgingold-cern/sf2
complete support for microsemi smartfusion2 and igloo2bar
Diffstat (limited to 'techlibs/sf2/tests/test_arith.ys')
| -rw-r--r-- | techlibs/sf2/tests/test_arith.ys | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/sf2/tests/test_arith.ys b/techlibs/sf2/tests/test_arith.ys new file mode 100644 index 000000000..da7b96602 --- /dev/null +++ b/techlibs/sf2/tests/test_arith.ys @@ -0,0 +1,22 @@ +# Our implementation +read_verilog ../arith_map.v +read_verilog ../cells_sim.v +read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v +rename \$__SF2_ALU gate +hierarchy -top gate -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5 +flatten +opt +write_verilog gate.v + +# The reference +read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v +rename \$alu gold +hierarchy -top gold -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5 +flatten +proc +clean +write_verilog gold.v + +read_verilog gate.v +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter |