diff options
| author | Tristan Gingold <tristan.gingold@cern.ch> | 2021-11-24 17:09:59 +0100 |
|---|---|---|
| committer | Tristan Gingold <tristan.gingold@cern.ch> | 2022-08-31 08:40:44 +0200 |
| commit | 0f6cf8b8e4c3574aefae9f613161a5a5648fb04f (patch) | |
| tree | 3752f2f66d1f8e7cb2858d32336eefb3027a2a26 /techlibs/sf2/tests | |
| parent | c25f3ff3df8ec0c6979af6fa938716e461c8261b (diff) | |
| download | yosys-0f6cf8b8e4c3574aefae9f613161a5a5648fb04f.tar.gz yosys-0f6cf8b8e4c3574aefae9f613161a5a5648fb04f.tar.bz2 yosys-0f6cf8b8e4c3574aefae9f613161a5a5648fb04f.zip | |
sf2: add a test for $alu gate
Diffstat (limited to 'techlibs/sf2/tests')
| -rw-r--r-- | techlibs/sf2/tests/test_arith.ys | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/sf2/tests/test_arith.ys b/techlibs/sf2/tests/test_arith.ys new file mode 100644 index 000000000..da7b96602 --- /dev/null +++ b/techlibs/sf2/tests/test_arith.ys @@ -0,0 +1,22 @@ +# Our implementation +read_verilog ../arith_map.v +read_verilog ../cells_sim.v +read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v +rename \$__SF2_ALU gate +hierarchy -top gate -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5 +flatten +opt +write_verilog gate.v + +# The reference +read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v +rename \$alu gold +hierarchy -top gold -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5 +flatten +proc +clean +write_verilog gold.v + +read_verilog gate.v +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter |