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| author | R. Ou <rqou@robertou.com> | 2020-02-16 20:25:46 -0800 |
|---|---|---|
| committer | R. Ou <rqou@robertou.com> | 2020-02-16 20:25:46 -0800 |
| commit | 6a0682f5a0148949beacad0eb93ec5b754bf29cd (patch) | |
| tree | decc145a7bc6e32f684dfcbcb700cb06c93137c0 /techlibs/sf2 | |
| parent | cd60f079d6c96e1d8a00c3c081fab1148d432b44 (diff) | |
| download | yosys-6a0682f5a0148949beacad0eb93ec5b754bf29cd.tar.gz yosys-6a0682f5a0148949beacad0eb93ec5b754bf29cd.tar.bz2 yosys-6a0682f5a0148949beacad0eb93ec5b754bf29cd.zip | |
coolrunner2: Separate and improve buffer cell insertion pass
The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
Diffstat (limited to 'techlibs/sf2')
0 files changed, 0 insertions, 0 deletions