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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-15 10:55:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-15 10:55:27 +0100 |
| commit | 6c5049f016538e887476bb66d3f653155fa354ff (patch) | |
| tree | 591a28af00e484bd18ea0a0ad63bedf90a031950 /techlibs/sf2 | |
| parent | 1d82a88e948e614ada66b0fd59e9cc0aa569afae (diff) | |
| download | yosys-6c5049f016538e887476bb66d3f653155fa354ff.tar.gz yosys-6c5049f016538e887476bb66d3f653155fa354ff.tar.bz2 yosys-6c5049f016538e887476bb66d3f653155fa354ff.zip | |
Fix handling of $shiftx in Verilog back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/sf2')
0 files changed, 0 insertions, 0 deletions