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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-09 14:33:37 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-09 14:33:37 -0700 |
| commit | 3e368593eb22d16de60c44ea721ca146082d3472 (patch) | |
| tree | 74765bfb250caf957e792e0f81b2fd0775d33cd3 /techlibs/xilinx/Makefile.inc | |
| parent | fd88ab5c834a45f4828a03fe7722b321e5f7c032 (diff) | |
| download | yosys-3e368593eb22d16de60c44ea721ca146082d3472.tar.gz yosys-3e368593eb22d16de60c44ea721ca146082d3472.tar.bz2 yosys-3e368593eb22d16de60c44ea721ca146082d3472.zip | |
Add cells.lut to techlibs/xilinx/
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 9937c0c9c..432bb0770 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) |