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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-06 08:44:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-06 08:44:30 +0200 |
| commit | 4389d9306ecb64df29115027ad9a948d852448bd (patch) | |
| tree | 120ad8f6c7488f7d6c886473f7d66aade9654d23 /techlibs/xilinx/Makefile.inc | |
| parent | c0e2b3eb11657fc9a4eb9f04073a4f5f8affaa55 (diff) | |
| download | yosys-4389d9306ecb64df29115027ad9a948d852448bd.tar.gz yosys-4389d9306ecb64df29115027ad9a948d852448bd.tar.bz2 yosys-4389d9306ecb64df29115027ad9a948d852448bd.zip | |
Added Xilinx bram black-box modules
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 9af7b58f3..18f6764ea 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -5,5 +5,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) |