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| author | Clifford Wolf <clifford@clifford.at> | 2018-03-07 17:31:07 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-07 17:31:48 +0100 |
| commit | 6991c132b501ebb48fa5dd1b0f995bb544261556 (patch) | |
| tree | 5b43209f73172cb8412ee7831dc42a7da9c78f4d /techlibs/xilinx/Makefile.inc | |
| parent | 73c01dca6540e389393c0ec606fd3c9c4b6d95c4 (diff) | |
| download | yosys-6991c132b501ebb48fa5dd1b0f995bb544261556.tar.gz yosys-6991c132b501ebb48fa5dd1b0f995bb544261556.tar.bz2 yosys-6991c132b501ebb48fa5dd1b0f995bb544261556.zip | |
Add Xilinx RAM64X1D and RAM128X1D simulation models
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index d4d4bd09a..887ea27d9 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -27,7 +27,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut2lut.v)) |