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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 12:22:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 7cd3f4a79bde6dbe2cd7f90d0a4996aebe70fd10 (patch) | |
| tree | 103caee23d30a3a81fe1a56cd88dd5523df486c2 /techlibs/xilinx/Makefile.inc | |
| parent | bb840cca9cd62ad59b2054049e979263325ba664 (diff) | |
| download | yosys-7cd3f4a79bde6dbe2cd7f90d0a4996aebe70fd10.tar.gz yosys-7cd3f4a79bde6dbe2cd7f90d0a4996aebe70fd10.tar.bz2 yosys-7cd3f4a79bde6dbe2cd7f90d0a4996aebe70fd10.zip | |
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 9984290a6..d4d863831 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -54,8 +54,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) |